1. Field of the Invention
This invention relates generally to a method and apparatus for testing computers and processors during manufacture, and more particularly, to a method and apparatus for using software and signature analysis tools to perform tests.
2. Description of the Related Art
The testing process is an important part of the manufacture of micro-processors and computers. A modern processor may have over three million transistors and even more internal connections. In devices of such complexity, it is difficult to test all combinations of data and operations of the device and to ensure the absence of defects therein.
FIG. 1 shows a simple processor 18 that will be employed to illustrate a "faulty unit" signature test. The processor 18 is composed of several units, including: an arithmetic logic unit (ALU) 20, an address translation unit (ATU) 22, a floating point unit (FPU) 24, and an instruction decode unit (IDU) 26. The ALU 20, ATU 22, FPU 24, and IDU 26, have a number of control and/or data connections 28, 30, 32. A bus unit 34 connects the processor 18 to memory and input/output ports (I/O) (both not shown). The units 20, 22, 24, 26 of the processor 18 communicate with the memory and I/O by bus lines 36, 38.
FIG. 2 illustrates a prior art test apparatus 50 for performing a signature based "faulty unit" test on the processor 18 of FIG. 1. Each functional unit 20, 22, 24, 26 of the processor 18 is individually connected to parallel input terminals (not shown) of a multiple input signature register (MISR) 42, 44, 46, 48. Each MISR 42, 44, 46, 48 ordinarily has one parallel input terminal for each output terminal of the functional unit 20, 22, 24, 26 connected thereto (not shown). During the test, each MISR 42, 44, 46, 48 accumulates data from the associated functional unit 20, 22, 24, 26 in response to receiving a clock pulse on a line 59 connected to a clock 49. The MISR's 42, 44, 46, 48 add new data to data stored during prior clock pulses through an operation that is specified by a preselected polynomial and that reproducibly gives a single signature number.
The signature number ordinarily has one binary bit for each parallel input terminal, and each bit thereof is affected by data from all parallel input terminals of the MISR. Signature testing uses the signature number like a parity bit. The signature number is compared to a reference signature number, and an error is reported if any bit does not match. For signature numbers having many bits, the risk of "aliasing" or false matches is reduced, because the probability of aliasing is approximately 2.sup.-D where D is the number of bits of the signature number provided that the polynomial is constructed correctly.
Since each of the functional units 22, 24, 26, 28 of the processor 18 is connected directly to a separate MISR 42, 44, 46, 48, the test apparatus 50 concurrently and individually tests the various functional units 22, 24, 26, 28, of the processor 18. The MISR's 42, 44, 46, 48 have serial input terminals 51, 52, 53, 54 and output terminals 55, 56, 57, 58 for inputting initial signature patterns and outputting final signature numbers. The MISR's 42, 44, 46, 48 also have control lines 60 for controlling respective input terminals, output terminals, and data accumulation. The test apparatus 50 may be permanently embedded on the die holding the processor 18 itself.
FIG. 3 illustrates a prior art method 61 for performing a "faulty unit" test with the test apparatus 50 of FIG. 2. At a block 62, the sequential logic units (not shown), of each MISR 42, 44, 46, 48 are initialized to a predetermined state by serially inputting initial patterns through the input lines 51, 52, 53, 54. Though the exact form of the initial state is not essential, the reproducibility of the initial state is essential to the test method 61. At block 64, a second set of initial patterns, e.g., data and instructions, is placed in the sequential circuit elements such as registers, flip-flops, latches and buffers (not shown) of the functional units 20, 22, 24, 26 of the processor 18 itself. Typically, the initial patterns are placed in the functional units 20, 22, 24, 26 from input/output ports (not shown) and external devices (not shown) connected to the bus 36. Several clock cycles may be employed to set up the initial patterns in the processor 18 and MISR's 42, 44, 46, 48.
After setting up the initial state, signature data collection proceeds in loop-like fashion. At block 66, the processor 18 runs for a preselected number of clock cycles. Then, at block 68, the parallel input terminals of the MISR's 42, 44, 46, 48 are enabled by control signals on the lines 60, and data is taken from the functional units 22, 24, 26, 28 connected to each MISR 42, 44, 46, 48. At block 70, the input data is added to the data already stored in the individual MISR's 42, 44, 46, 48 in response to receipt of a pulse from the clock 49 on the clock lines 59. The cycles of running the processor 18, enabling the parallel input terminals of the MISR's 42, 44, 46, 48, and adding new data to data already stored in the MISR's 42, 44, 46, 48 as shown in blocks 66, 68, 70 are repeated for a predetermined number of clock cycles as measured by the clock 49. The cycles of data taking produce a single signature number at any time in each MISR 42, 44, 46, 48. After the predetermined number of clock cycles selected for the test, the signature number from each MISR 42, 44, 46, 48 is serially read from the output terminals 55, 56, 57, 58.
Since the initial states, cycle lengths, and number of data taking cycles are reproducibly controlled, the output signal of each MISR 42, 44, 46, 48 is a reproducible signature number. At block 72, the signature number from each MISR 42, 44, 46, 48 is compared with a reference signature number that would result from performing the same test on a properly functioning processor 18 of the same type. As block 74 illustrates the reference signature number is determined empirically by performing the test on a "good" processor 18 prior to performing any tests on "unknown" processors 18. If the signature number from the test does not match the reference signature number, the functional unit 22, 24, 26, 28 of the processor associated with the non-matching number is not operating correctly, and the processor 18 fails the test. If the test and reference signature numbers match, the associated processor 18 passes the test.
Though the "faulty unit" test detects many defects, the test cannot detect all defects that may be present in the processor. In particular, the "faulty unit" test focuses on defects of individual functional units 22, 24, 26, 28 of the processor 18. Typically, more than 99.9 percent of all processors that pass the "faulty unit" test may be defect free. Nevertheless, processors are expensive devices and quality control to a fraction of 0.1 percent is not sufficient for the high standards of the computer industry.
The "faulty unit" test and equivalent tests may miss system-level defects that lead to occasional problems when the processor runs software operating systems such as WINDOWS.RTM., UNIX.RTM., a disk operating system (DOS), or applications such as EXCEL.RTM., WORD.RTM., or paint programs and custom software written to check certain features. The system-level defects are not typically associated with one functional 20, 22, 24, 26 unit of the processor 18. Thus, the "faulty unit" test often is unable to detect them. Unfortunately, using the high level software itself to detect the system-level defects is also problematic, because complex software performs a variety of non-reproducible acts such as reading disks, responding to interrupt requests and reading system clocks in the course of normal operation. If the software performs non-reproducible acts, the output signals produced by running the software are not directly amenable to the detailed comparisons inherent in simple signature tests. Finally, tests for system-level defects that employ high level software without signature analysis are extremely time consuming and costly. Thus, industry standards demand the detection and elimination of processors having system-level, manufacturing defects, because such defects interfere with operating modern operating systems. Nevertheless, the present forms of inexpensive signature testing do not detect such defects.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.